Many modern electronic devices contain components that operate from different power supply voltages. For example, in a laptop computer, the data processor module may be powered by a +3.3 volt power supply while the disk drive(s) may be powered by a +5.0 volt power supply. This difference in operating conditions may cause problems for the module using the lower power supply voltage, particularly if the modules are coupled by a common bus. A condition known as reverse charge leakage occurs when a module applies a voltage to a common bus and the voltage creates a charge leakage path from the bus to the power supply of a module operating at a lower power supply voltage.
For instance, a +3.3 volt module using a PMOS pull-up transistor at its output to a bus applies a +3.3 volt gate voltage to turn off the PMOS transistor. However, if the bus is raised to +5.0 volts by a commonly connected +5.0 volt module, the PMOS transistor may be turned on, providing a conductive path from the bus to the +3.3 volt power supply rail. Since the back-gate of the +3.3 volt PMOS transistor is typically tied to +3.3 volts as well, the drain/back-gate diode of the device provides another conductive channel.
Another problem that occurs with modules operating under different power supply voltages is the potential for gate oxide breakdown when the low-power module is powered down (i.e., when the power supply is at 0 volts). For instance, in a +3.3 volt process, the maximum voltage allowed from the gate to the source or from the gate to the drain in any device is 4.6 volts. The maximum gate to back-gate voltage is 5.3 V. A+5.0 volt signal appearing on a common bus when the +3.3 volt module is powered down can create gate oxide voltages exceeding the 4.6 V level, leading to device failure.
U.S. Pat. No. 5,555,149, issued Sep. 10, 1996 to Wert et al., discloses an output buffer that prevents reverse charge leakage by using isolation transistors to block potential leakage paths. However, when the invention disclosed in U.S. Pat. No. 5,555,149 is powered down, it provides no protection against gate oxide breakdown. The teachings of U.S. Pat. No. 5,555,149 are hereby incorporated by reference into the present disclosure as if fully set forth herein.
U.S. Pat. No. 6,081,412, issued Jun. 27, 2000 to Wert et al., discloses an output driver protection circuit that avoids reverse charge leakage while preventing excessive gate oxide voltage development when powered down. The teachings of U.S. Pat. No. 6,081,412 are hereby incorporated by reference into the present disclosure as if fully set forth herein.
FIG. 1 illustrates prior art output driver circuit 100, which is illustrated and described in U.S. Pat. No. 6,081,412. Output driver circuit 100 generates a first reference voltage at node A at the output of transistor 125 and a second reference voltage at node C at the output of transistor 126. As is explained in greater detail in U.S. Pat. No. 6,081,412, the output driver protection circuit always provides power at node A. Under normal operating conditions, the voltage at node A of output driver circuit 100 is VDD (e.g., +3.3 volts). Under over-voltage conditions, the voltage at node A is equal to the PAD voltage minus some voltage drop determined by transistors 121-125. Under normal operating conditions, the voltage at node C of output driver circuit 100 is 0 volts. Under over-voltage conditions, the voltage at node C is equal to the voltage at node A.
In some electronic circuit designs, it may be necessary to provide additional protection by implementing protective logic gates that operate under over-voltage conditions and when the low power supply is zero volts. Preferably, these protective logic gates are capable of operating from the voltages provided by node A and node C in output driver circuit 100.